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EPF10K50 - Altera
Manufacturer:
Altera
ManyChip's Part#:
MC571924258
RoHS:
Lead free / RoHS Compliant
Datasheet:
Datasheet 3D Model
Description:
EMBEDDED PROGRAMMABLE LOGIC FAMILY
Stock Locations:
Availability:
206 pcs In Stock
MOQ:
1 pcs
Unit Price:
$ 0

Updated at 18/06/2025 10:30:15(UTC+8)

Certifications

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Description

This datasheet describes configuration devices for SRAM-based look-up table (LUT) devices.
Features
Configuration devices for SRAM-based LUT devices offer the following features:
■ Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
■ Easy-to-use four-pin interface
■ Low current during configuration and near-zero standby mode current
■ Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
■ Available in compact plastic packages
■ 8-pin plastic dual in-line (PDIP) package
■ 20-pin plastic J-lead chip carrier (PLCC) package
■ 32-pin plastic thin quad flat pack (TQFP) package
■ EPC2 device has reprogrammable flash configuration memory
■ 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
■ Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
■ Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
■ nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Show

EPF10K50 Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
	Show
RoHS	RoHS Compliant

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