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Description
Product Details
The ADG467 is an octal channel protector. The channel protector is placed in series with the signal path. The channel protector protects sensitive components from voltage transience in the signal path regardless if the power supplies are present or not. For this reason, the channel protectors are ideal for use in applications where correct power sequencing cannot always be guaranteed (for example, hot insertion rack systems) to protect analog inputs.
Each channel protector has an independent operation and consists of an N-channel MOSFET, a P-channel MOSFET, and an N-channel MOSFET, connected in series. The channel protector behaves just like a series resistor during normal operation, that is, (VSS \+ 1.5 V) < VIN < (VDD − 1.5 V). When a channel’s analog input exceeds the power supplies (including VDD and VSS = 0 V), one of the MOSFETs switches off, clamping the output to either VSS \+ 1.5 V or VDD − 1.5 V. Circuitry and signal source protection is provided in the event of an overvoltage or power loss. The channel protectors can withstand overvoltage inputs from −40 V to +40 V.
The ADG467 can operate off both bipolar and unipolar supplies. The channels are normally on when power is connected and open circuit when power is disconnected. With power supplies of ±15 V, the on resistance of the ADG467 is 62 Ω typical with a leakage current of ±1 nA maximum. When power is disconnected, the input leakage current is approximately ±0.5 nA typical.
The ADG467 is available in an 18-lead SOIC package and a 20-lead SSOP package.
Product Highlights
1. Fault Protection.
The ADG467 can withstand continuous voltage inputs from −40 V to +40 V. When a fault occurs due to the power supplies being turned off or due to an overvoltage being applied to the ADG467, the output is clamped. When power is turned off, current is limited to the microampere level.
2. Low Power Dissipation.
3. Low RON. 62 Ω typical.
4. Trench Isolation Latch-Up Proof Construction.
A dielectric trench separates the p- and n-channel MOSFETs thereby preventing latch-up.
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