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Updated at 01/11/2025 10:30:15(UTC+8)

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Description

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP110 is characterized for operation from –40°C to 85°C.

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CDCLVP110VF Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
Mounting Style	Surface Mount
Number of Pins	32 Pin
Case/Package	LQFP-32
Frequency	3.5 GHz
Supply Voltage (DC)	2.38V ~ 3.80V
Number of Outputs	10 Output
Supply Current	85.0 mA
Number of Circuits	1 Circuit
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2.375V ~ 3.8V
Supply Voltage (Max)	3.8 V
Supply Voltage (Min)	2.375 V
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Size-Length	7 mm
Size-Width	7 mm
Size-Height	1.4 mm
Operating Temperature	-40℃ ~ 85℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99
HK STC License	NLR

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