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Updated at 17/06/2025 10:30:15(UTC+8)

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Description

The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from V to fine tune the output delay from 0 to 60 ps.
Features
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Maximum Frequency > 1.2 GHz Typical
PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the ENbar Pin Will Force Q to Logic Low
D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
VBB Output Reference Voltage
Pb-Free Packages are Available

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MC100EP196 Specifications

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