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Updated at 31/10/2025 10:30:15(UTC+8)

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Description

The SN74HC164DR is a 8-bit parallel-out serial Shift Register features AND-gated serial inputs and an asynchronous clear (CLR\\) input. The gated serial (A and B) inputs permit complete control over incoming data, a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. clocking occurs on the low-to-high-level transition of CLK.
Outputs can drive up to 10 LSTTL loads
80µA Maximum low power consumption
Typical tpd = 20ns
±4mA Output drive at 5V
1µA Maximum low input current
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
Green product and no Sb/Br

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SN74HC164DR Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
Mounting Style	Surface Mount
Number of Pins	14 Pin
Case/Package	SOIC-14
Supply Voltage (DC)	2.00V ~ 6.00V
Operating Voltage	2V ~ 6V
Number of Outputs	8 Output
Number of Circuits	1 Circuit
Number of Positions	14 Position
Number of Bits	8 Bit
Voltage Nodes	6.00 V, 5.00 V, 2.00 V
Output Current Drive	-1.00 mA
Number of Inputs	2 Input
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 6V
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
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Size-Length	8.65 mm
Size-Width	3.91 mm
Size-Height	1.58 mm
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99
HK STC License	NLR

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SN:H6.49743LO54654V52Q0QC0S0

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