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Updated at 17/06/2025 10:30:15(UTC+8)

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Description

The TPS3813K33QDBVRQ1 is a Supervisory Circuit with active-low open-drain output. The supervisory circuit provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems. During power on, the /RESET pin is asserted when the supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps the /RESET pin active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive (high) state to ensure proper system reset. The delay time (td) of 25ms typical, begins after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. It has a fixed-sense threshold voltage (VIT) set by an internal voltage divider.
Window-watchdog with programmable delay and window ratio
power-ON reset generator
9µA Typical supply current
Green product and no Sb/Br

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TPS3813K33QDBVRQ1 Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
Mounting Style	Surface Mount
Number of Pins	6 Pin
Case/Package	SOT-23-6
Supply Voltage (DC)	2.00V (min)
Supply Current	0.025 mA
Number of Positions	6 Position
Power Dissipation	0.437 W
Quiescent Current	9.00 µA
Threshold Voltage	2.93 V
Reset Threshold Voltage (Min)	2.87 V
Reset Threshold Voltage (Max)	3 V
Operating Temperature (Max)	125 ℃
Operating Temperature (Min)	-40 ℃
Power Dissipation (Max)	437 mW
Supply Voltage (Max)	6 V
Supply Voltage (Min)	2 V
	Show
Operating Temperature	-40℃ ~ 125℃
Product Lifecycle Status	Active
Packaging	Tape & Reel (TR)
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2014/12/17
ECCN Code	EAR99

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SN:H2.76962LO11064V31Q0QC0S0

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