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Updated at 17/06/2025 10:30:15(UTC+8)

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Description

General description
The 74AHC573; 74AHCT573 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.
The 74AHC573; 74AHCT573 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches.
Features and benefits
 Balanced propagation delays
 All inputs have a Schmitt trigger action
 Common 3-state output enable input
 Functionally identical to the 74AHC373; 74AHCT373
 Inputs accept voltages higher than VCC
 Input levels:
For 74AHC573: CMOS input level
 For 74AHCT573: TTL input level
 ESD protection:
HBM EIA/JESD22-A114E exceeds 2000 V
 MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
 Multiple package options
 Specified from40℃ to +85℃ and from 40℃ to +125℃

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74AHC573 Specifications

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- Delivery date: usually 2 to 7 working days.
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- Carefully inspected and packed by ManyChip warehouse
- Vacuum packaging
- Anti-static packaging
- Shockproof foam
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