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Updated at 31/10/2025 10:30:15(UTC+8)

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Description

The SN74AHC74N is a dual positive-edge-triggered D-type Flip-flop with clear and preset. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Latch-up performance exceeds 250mA per JESD 17
ESD Protection exceeds JESD 22

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SN74AHC74N Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
Mounting Style	Through Hole
Number of Pins	14 Pin
Case/Package	DIP-14
Frequency	115 MHz
Digital Logic Level	CMOS
Supply Voltage (DC)	2.00V ~ 5.50V
Number of Outputs	1 Output
Output Voltage	≤5.50 V
Output Current	8 mA
Number of Circuits	2 Circuit
Number of Channels	2 Channel
Number of Positions	14 Position
Clock Speed	115 MHz
Number of Bits	2 Bit
Propagation Delay Max (tpd)	10.5 ns
Polarity	Non-Inverting, Inverting
Voltage Nodes	5.00 V, 3.30 V
Input Capacitance	2 pF
Output Current Drive	-1.00 mA
Number of Inputs	1 Input
Operating Temperature (Max)	85 ℃
Operating Temperature (Min)	-40 ℃
Supply Voltage	2V ~ 5.5V
Supply Voltage (Max)	5.5 V
Supply Voltage (Min)	2 V
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Operating Temperature	-40℃ ~ 125℃ (TA)
Product Lifecycle Status	Active
Packaging	Tube
RoHS	RoHS Compliant
Lead-Free Status	Lead Free
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	EAR99

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