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Updated at 01/11/2025 10:30:15(UTC+8)

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Description

The DP83865DVH is a fully-featured Physical-layer Transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols. The DP83865 is an ultra-low power version of the DP83861 and DP83891. It uses advanced 0.18um, 1.8V CMOS technology, fabricated at National Semiconductor"s South Portland, Maine facility. It is designed for easy implementation of 10/100/1000Mbps Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII). It is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
Ultralow power consumption typically 1.1W
Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
Speed fallback mode to achieve quality link
Cable length estimator
User programmable interrupt
Supports JTAG (IEEE1149.1)

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DP83865DVH Specifications

Attribute	Attribute Value

Datasheet	Datasheet
3D Model	3D Model
Mounting Style	Surface Mount
Number of Pins	128 Pin
Case/Package	QFP-128
Supply Voltage (DC)	1.71V (min)
Supply Current	430 mA
Number of Channels	1 Channel
Number of Positions	128 Position
Data Rate	1.00 Gbps
Operating Temperature (Max)	70 ℃
Operating Temperature (Min)	0 ℃
Supply Voltage	1.71V ~ 3.465V
Supply Voltage (Max)	2.625 V
Supply Voltage (Min)	2.375 V
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Cable Length	100 m
Operating Temperature	0℃ ~ 70℃
Product Lifecycle Status	Active
Packaging	Tray
RoHS	Non-Compliant
Lead-Free Status	Contains Lead
REACH SVHC Compliance	No SVHC
REACH SVHC Compliance Edition	2015/06/15
ECCN Code	5A991.b.1

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